Increases in density of integrated circuits impose increasing challenges on the testing of such circuits. A significant factor contributing to the difficulty in testing dense integrated circuits (chips) is the inaccessibility of particular circuits within the chip from the chip pins. The lack of direct access to many circuits requires development of test strategies to indirectly access such circuits. A known technique for accessing circuitry embedded within a chip is by use of scan chains within the chip. Aspects of scan chains and scan testing are described in "Logic Design Principles" by E. J. McCluskey 1986, Prentice Hall, N.J.
One of the drawbacks to employing scan chains for testing embedded circuitry is that scan data serialization leads to low bandwidth testing and prevents the application of test vectors and measurement of circuit response on a per cycle basis. For example in scan-based testing, the state data desired to start an operation must be scanned into position. The desired operation must be performed and then the data in the scan chain must be scanned out of the chip. Such a procedure is useful, but can be very time consuming if multiple operations need to be tested. What is needed therefore is an improved testing mechanism that facilitates testing of embedded circuits in an integrated circuit, allowing new test data to be applied and response measured every clock cycle.